Read clock pulse controller

ABSTRACT

A clock pulse control device for address allocation of a read-only memory in a small size sequence controller in which data stored in the read-only memory are read out sequentially to operate an output relay during a time interval in accordance with the stored data, and the relay controls a load. Clock pulses generated by a frequency-dividing clock pulse generator (30) are applied to presetable down counters (33) and (34) in which the clock pulses are divided down to pulses each having a time period corresponding to the preset value. The divided pulses are applied to a binary counter (29). The outputs of the binary counter (29) are delivered to the read-only memory provided outside from address lines (Q1)-(Q7) via a connector (10) to allocated addresses of the read-only memory sequentially. Predetermined data are stored in the read-only memory in advance and the data of the allocated addresses are delivered to operate the output relay. The time period of the pulses to be applied to the binary counter (29) may be varied by changing-over a selecting switch (6) or changing the preset value of the presettable down counters (33) and (34).

TECHNICAL FIELD

The present invention relates to a read clock pulse controller forapplying read clock pulses to a read-only sequence controller having anEPROM in an output relay unit.

BACKGROUND ART

A conventional sequence controller has a writing means and a readingmeans. However, the writing means is not used after a necessary data hasbeen written in. Therefore the sequence controller having the writingmeans which is scarcely used is very unreasonable and expensive. Inorder to remove such disadvantages, it should be attempted to provide asequence controller having a single function.

DISCLOSURE OF THE INVENTION

In accordance with the present invention, the sequence controller isdivided into a write-only sequence controller and a read-only sequencecontroller. The write-only sequence controller is provided for writingdata in an EPROM or MASK ROM to be attached thereto. The read-onlysequence controller is adapted to mount the EPROM or ROM and to producean output of the data in the EPROM or ROM.

Since data may be written in a plurality of EPROMs by one write-onlysequence controller, an economical control system may be provided.Accordingly, only one write-only sequence controller can be used forwriting data in EPROMs for a plurality of read-only sequencecontrollers, even if 1000 units of read-only sequence controller.

Further, the read-only sequence controller is divided into

(A) an output relay control unit, and

(B) a read clock pulse control unit.

The output relay control unit has an output relay unit to which theEPROM is attached. By applying read clock pulses to the output relayunit, the output is produced from the output relay unit.

A standard EPROM of the read-only sequence controller of the presentinvention is a type of N words×8 bits and the output relay compriseseight units.

Designating the read-only sequence controller as A and the read clockpulse controller as B, parallel 8-process outputs are obtained by A+B,16-process outputs are obtained by 2A+B, 24-process by 3A+B, 32-processby 4A+B and 80-process by 10A+B. As will be seen, increase of theprocess may be achieved by just increasing the number of A.

The read-only sequence controller of the present invention may be madeinto a light device having a weight of 280 g and into a compact size.Thus, economical control may be provided for automatization of machineand for energy saving.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a plan view of a read clock pulse controller according tothe present invention;

FIG. 2 shows a perspective view of the controller;

FIG. 3 shows a cross sectional view of the controller;

FIG. 4 shows a circuit of a read clock pulse controller;

FIG. 5 shows a circuit of contact relay system connected to the readclock pulse controller of the present invention;

FIG. 6 shows a circuit of contactless relay system; and

FIG. 7 shows a perspective view of a read-only sequence controllerconnected to the read clock pulse controller of the present invention.

BEST MODE FOR EMBODYING THE INVENTION

Referring to FIG. 1, a case of the read clock pulse controller comprisespanel plates 1 and 2 and a pair of covers 3 made of metal plate. Presetcode switches 4 and 5 display 2 digits of two figures as the sequencecycle time. Numeral 6 is a cycle time select switch, 7 is a startswitch, 8 is a stop switch. A ribbon cable 9 is connected to an outsideoutput relay unit through a connector 10. Numeral 11 is a pilot lamp. Aconnector 12 is connected to a supply voltage DC. An abnormalitydetecting connector 13 is connected to an outer abnormality detectingcircuit. An auto-start connector 14 is connected to an outside remotecontroller and an auto-stop connector 15 is connected to the outsideremote controller. A connector 16 is connected to an outside remotecontrol manual start switch. A connector 17 is connected to an outsideremote control manual stop switch. Numeral 18 designates a reset switch.When a changeover switch 19 is turned OFF, one cycle of operation isdone, while the switch 19 is turned ON, the cycle is repeated.

As shown in FIGS. 2 and 3, a pair of supporting projections 21 for aprinted-wiring board 20 and projections 22 for covers 3 are formed inpanels 1 and 2. Opposite end portions of each cover 3 are outwardlyinclined and bent at ends 23 to reinforce the portions. Both covers 3are abutted at bent ends 23 and supported between the projections 22 andsecured by L-shaped members 24 and screws 25.

In order to generate the read clock pulses, a first preset code switches4 and 5 and the select switch 6 are operated to select a necessary cycletime. If the select switch 6 is set to 0.1 SEC, digits "58" shown inFIG. 1 means that a cycle time of 5.8 seconds is provided. If the selectswitch is set to SEC, the cycle time is 58 seconds. Further, setting theselect switch to MIN, makes the cycle time of 58 minutes. Each of thedigits of the preset code switch can be changed from "0" to "9".Accordingly, 297 kinds of cycle time are available in total.

Referring to FIG. 4, ribbon cable 9 is connected to the output relayunit. The cycle time is set, the changeover switch 19 is set toone-cycle side (OFF), and then the start switch 7 is depressed. A signal"0" is applied to a 3-input NAND gate 26 through a filter circuit and agate protective circuit comprising resistors, a capacitor, and diodes.By the output "1" from the gate 26, a one-shot pulse "0" appears at theoutput of a one-shot pulse generating circuit 27. This signal isinverted through an inverter 28 to a one-shot pulse "1". This one-shotpulse "1" is applied

(A) to a reset R of a binary counter 29 to reset it to the zero state,

(B) to a reset R of a clock pulse generating circuit 30 comprising afrequency dividing circuit to reset it to the zero state, and

(C) to inputs PE of presettable counters 33 and 34 through an inverter31 and a 2-input NAND gate 32 to preset the digit "58" of preset codeswitches 4 and 5 in counters 33 and 34.

Outputs of crystal oscillator 35 is divided by the clock pulsegenerating circuit 30 into 1000 Hz, 100 Hz, and 5/3 Hz as clock pulses.Any one of these clock pulses is selected by the select switch 6.

The clock pulses are applied to clock lines C of the presettablecounters 33 and 34 through the select switch 6. Preset lines P1, P2, P3and P4 of the presettable counters are connected to BCD lines of presetcode switches 4 and 5. Here it is assumed that each of presettablecounters 33 and 34 is used as a down counter by connecting the UP/DOWNinput thereof to the ground (not shown).

Each time one clock pulse is applied to the presettable counter 33, thecount therein decreases by one. When the count goes to zero, the upperfigure is changed from "5" to "4" and the lower figure is changed to"9". When 58 clock pulses are applied to the presettable counters, bothinputs of a 2-input NOR gate 36 go to a "0". Thus, the 2-input NOR gateproduces one read clock pulse which is applied to the clock line C ofthe binary counter 29 through an inverter 37. Accordingly, the binarycounter 29 produces outputs through address lines Q1, Q2 . . . Q7. Theoutputs appear on the counter 10 after being amplified by buffers 38 andpulled up by resistors 39.

On the other hand, the output of the 2-input NOR gate 36 causes a2-input NAND gate 40 to produce "0" when an inverter 41 produces output"1" by a negative going clock input. Thus, the presettable counter ispreset through the 2-input NAND gate 32. At the same time, the "58" ofpreset code switches 4 and 5 are preset again in presettable counters 33and 34.

Thereafter, every time 58 clock pulses are applied to presettablecounters, one read clock pulse is generated. Time of one cycle isdecided by the number of read clock pulse. Operation in the case of 100clock pulses in one cycle will be explained hereinafter.

In order to produce the one-cycle end signal upon 100 read clock pulses,address lines Q3, Q6 and Q7 of the binary counter 29 are selected forthe inputs of a 3-input NAND gate 41. Since the binary number of "100"is 1100100, when the 100 read clock pulses are applied to the input ofthe binary counter 29, outputs on the address lines Q3, Q6 and Q7 go to"1" and the 3-input NAND gate 41 produces a one-cycle end signal "0". Bythe one-cycle end signal.

(A) a "1" is applied through a 3-input NAND gate 42 to the CIN line ofthe presettable down counter 33 and stops counting,

(B) a "0" is applied to a set input S of a first flip-flop 45 through a2-input NAND gate 43 and an inverter 44, and the output Q "1" is appliedthrough the buffer 38, the connector 10, and the ribbon cable 9 to theCS/WE of the EPROM of the read-only sequence controller and the EPROMbecomes to the non-selection state.

Therefore, the presettable counter stops counting and the EPROM stopsproducing the output, so that the machine to be controlled by thissystem stops after 5.8 seconds operation. By such operation, inspectionof operation of the machine may be taken place. If the changeover switch19 is set to ON side, a one cycle end signal "0" is applied to the3-input NAND gate 26. This causes the same result as depressing thestart switch. Thus,

(A) the binary counter 29 is cleared,

(B) the frequency dividing clock pulse generating circuit 30 is cleared,

(C) a digit of the preset code switch is preset in the presettable downcounter,

(D) a "0" enters in the reset R of the first flip-flop 45 and the outputQ "0" is applied to the CS/WE of the EPROM of the read-only sequencecontroller and the EPROM becomes to the selection state.

Then, the presettable counter starts counting and read clock pulses areapplied to the binary counter, so that address cells of the EPROMcorresponding to address lines Q1, Q2 . . . Q7 are addressed to produceprograming data. Thus, the machine operation is repeatedly continued atthe cycle time of 5.8 seconds.

In order to stop the operation, the switch 19 is turned off, so that theoperation stops at the end of one cycle. Depressing the stop switch 8, a"0" is applied to the set input S of a second flip-flop 46. A "0" of theoutput Q is applied to the 3-input NAND gate 42 to produce an output "1"which causes the stop of counting of the presettable counters.

Describing an abnormality detecting circuit, a collector of a phototransistor of a photo coupler 48, which is pulled up by a resistor 47,is connected to the ground through an emitter, and a light emittingdiode is connected to a connector 13 to which an outer abnormalitydetecting circuit is connected. When the detecting circuit detects anyabnormality, the photo coupler 48 turns on. Accordingly, a "0" isapplied to the 3-input NAND gate 42, so that the presettable downcounter stops counting and the machine stops.

In the case that the system of the present invention is used forcontrolling manufacturing machines, an unfinished work may be easilyremoved from the machine in the stop condition and inspection and repairof the system may be done.

If the start switch 7 is depressed after inspection and repair, the holdcondition by first and second flip-flop is released and operation isrestarted. The connector 15 connected to the connector 13 is to beconnected to an outside controller for stopping the system. When theoutside controller applies a signal to the system, the photo coupler 48is turned on to stop the operation of the system.

A collector of a photo transistor of a photo coupler 50, which is pulledup by a resistor 49, is connected to the ground through the emitter, andthe light emitting diode is connected to the connector 14 by means ofthe diodes of their respective polarities as shown and a resistor. Whenan outside controller emanates a signal, the photo coupler 50 is turnedON and a signal "0" is applied to the 3-input NAND gate 26. This causesthe same result as depressing the start switch 7. Thus, the controllerstarts the operation at the cycle time of 5.8 seconds. That is theconnector 14 is connected to a remote control start circuit and theconnector 15 is connected to a remote control stop circuit.

Describing about a manual remote control circuit, the connector 16 isconnected to both sides of the start switch 7 and to an outside startswitch 51. The connector 17 is connected to both sides of the stopswitch 8 and to an outside stop switch 52. System supply voltage isobtained by an outside supply voltage through the connector 12.

Referring to FIG. 5 showing a contactless relay system, a supply voltageDC from an external power source is applied to V_(DD), V_(BB), V_(CC),and V_(SS) of an EPROM 53 through a connector 54. When the start switch7 of the read clock pulse controller is depressed, an input signal "0"is applied to CS/WE of the EPROM, so that the EPROM is changed toselection state. Then, address pulses in synchronism with read clockpulses are applied to address lines A1, A2 . . . A7 in the EPROM 53through the ribbon cable 9, connector 55 and a buffer 56, so that datain the EPROM 53 are produced from data outputs D1, D2 . . . D8 inparallel. Since driving circuits for eight output relays are the sameconstruction, explanation about the driving circuit for the No. 1 outputrelay will be made hereinafter.

The signal "1" appeared on the output D1 in the EPROM 53 is inverted to"0" by an inverter 57. The current flows from V_(CC) between inputs band a so that the contactless relay 58 is turned on to drive a load 59.When the output of the output D1 goes to "0", the contactless relay 58turns off so that driving of the load stops.

Referring to FIG. 6 showing a contact relay system, a supply voltage DCfrom an external power source is applied to V_(DD), V_(BB), V_(CC), andV_(SS) of the EPROM 53 through a connector 54. When the start switch 7of the read clock pulse controller is depressed, an input signal "0" isapplied to CS/WE of the EPROM, so that the EPROM is changed to selectionstate. Then, address pulses in synchronism with read clock pulses areapplied to address lines A1, A2 . . . A7 in the EPROM 53 through theribbon cable 9, connector 55 and a buffer 56, so that data in the EPROM53 are produced from data outputs D1, D2 . . . D8 in parallel. Theoutput data are applied to coils 62 of reed relays 61 through inverters57 to control corresponding output relays 60.

Since driving circuits for eight output relays are the sameconstruction, explanation about the driving circuit for the No. 1 outputrelay will be made hereinafter. The signal "1" appeared on the output D1in the EPROM 53 is inverted to "0" by the inverter 57. The current flowsfrom V_(CC) through the coil 62 of the reed relay 61 so that the reedrelay 61 is excited to turn on contacts thereof. Thus, current flowsfrom the terminal AC to the coil 63 of the output relay 60 to turn onthe relay 60 to drive load 59 connected to the output relay 60. When theoutput of the output D1 goes to "0", the reed relay 61 turns off. Thus,the output relay 60 turns off so that driving of the load stops.

In the circuit of FIG. 6, although a reed switch circuit is used as anisolation circuit between DC and AC, another isolation circuit, such asa photo-coupler circuit, photo-thyristor circuit or Cds circuit, may beemployed.

PROBABILITY OF INDUSTRIAL EXPLITATION

The read clock pulse controller of the present invention has a lightweight of 280 g. Therefore, the system is economical. The controller ofthe present invention can drive ten or more read-only sequencecontrollers, each of which has 8K bits (or 16K bits) memories. Thus, itis possible to automatize any kinds of machine, apparatus or system in awide field and to save the energy.

I claim:
 1. A read clock pulse controller for a read only sequencecontroller for a read-only memory comprising: a read clock pulsegenerating circuit (30); a select switch (6) for selecting the frequencyof the read clock pulse; a presettable counter (33, 34) for counting theread clock pulse; a preset code switch (4, 5) for selecting the numberof the read clock pulses counted by said presettable counter; a binarycounter (29) connected to the output of said presettable counter; saidpresettable counter increments said binary counter by one whenever thepresetted number of read clock pulses have been counted and the outputof said binary counter is connected to the address lines of saidread-only memory; a start switch (7) to initiate counting by applying asignal to a gate circuit (26); said gate circuit generating a signal toreset said binary counter to the zero state, to reset said clock pulsegenerating circuit to the zero state, and to preset the value in saidpresettable counter; a circuit means connected to an outer abnormalitydetecting circuit for generating a signal for inhibiting the countingoperation of said presettable counter when an abnormality is detected bysaid outer abnormality detecting circuit.
 2. The read clock pulsecontroller of claim 1 wherein an end signal is generated by binarycounter (29) after a selected number of pulses, said end signal isapplied to the presettable counter (33,34) to stop counting.